onnx2versal
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Conv2DKernels
Collaboration diagram for Conv2DKernels:

Classes

class  ConvReluScalar< INP_H, INP_W, OUT_W, OUT_W_PAD, STEP_H, STEP_W, B, C, M, KH, KW, GROUP, IS_RELU >
 Scalar implementation for BCHW, stores weights and biases, requires GROUP==1, ConvReluScalar<28,28,24,24,1,1,1,2,4,5,5,1,1> total = 368812 ConvReluScalar<24,24,10,10,2,2,1,2,4,5,5,1,1> total = 64413 ConvReluScalar<26,26,24,24,1,1,1,2,4,3,3,1,1> total = 159087. More...
 
class  Conv5x5on8Relu< INP_H, INP_W, OUT_W, OUT_W_PAD, STEP_H, STEP_W, B, C, M, KH, KW, GROUP, IS_RELU >
 Vector implementation for 5x5 BCHW, stores weights and biases, requires KH==KW==5, INP_W%4==0, OUT_W_PAD%8=0, STEP_H==STEP_W==1, GROUP==1, assumes weights are padded to MxCx5x8, Conv5x5on8Relu<28,28,24,24,1,1,1,2,4,5,5,1,1> total = 21401. More...
 
class  ConvHx4Relu< INP_H, INP_W, OUT_W, OUT_W_PAD, STEP_H, STEP_W, B, C, M, KH, KW, GROUP, IS_RELU >
 Vector implementation for 3x3 BCHW, stores weights and biases, requires KW<=4, INP_W%4==0, OUT_W_PAD%8=0, STEP_H==1, STEP_W==1, GROUP==1, assumes weights are padded to MxCx12, ConvHx4Relu<26,28,24,24,1,1,1,2,4,3,3,1,1> total = 10603. More...
 
class  Conv1x1Relu< INP_H, INP_W, OUT_W, OUT_W_PAD, STEP_H, STEP_W, B, C, M, KH, KW, GROUP, IS_RELU >
 Vector stream implementation for BCHW, stores weights and biases, requires KH==KW==1, INP_W%4==0, OUT_W_PAD%(8|4)==0, STEP_H==1|2, STEP_W==1|2, GROUP==1, Conv1x1Relu<24,24,24,24,1,1,1,2,4,1,1,1,1> total = 3617. More...
 
class  ConvReluScalarStream< INP_H, INP_W, OUT_W, OUT_W_PAD, STEP_H, STEP_W, B, C, M, KH, KW, GROUP, IS_RELU >
 Scalar stream implementation for BCHW, stores biases, requires GROUP==1, ConvReluScalarStream<26,28,24,24,1,1,1,2,4,3,3,1,1> total = 109354 ConvReluScalarStream<24,24,11,12,2,2,1,2,4,3,3,1,1> total = 23387. More...
 
class  ConvHx8ReluStream< INP_H, INP_W, OUT_W, OUT_W_PAD, STEP_H, STEP_W, B, C, M, KH, KW, GROUP, IS_RELU >
 Scalar stream implementation for BCHW, stores biases, requires GROUP==1, ConvHx8ReluStream<28,28,24,24,1,1,1,2,4,5,5,1,1> total = 24133. More...
 
class  ConvHx4ReluStream< INP_H, INP_W, OUT_W, OUT_W_PAD, STEP_H, STEP_W, B, C, M, KH, KW, GROUP, IS_RELU >
 Vector stream implementation for BCHW, stores biases, requires KW<=3, INP_W%4==0, OUT_W_PAD%(8|4)==0, STEP_H==1|2, STEP_W==1|2, GROUP==1, ConvHx4ReluStream<26,28,24,24,1,1,1,2,4,3,3,1,1> total = 13734 ConvHx4ReluStream<26,28,24,24,1,1,1,2,4,3,3,2,1> total = 8904 ConvHx4ReluStream<24,24,11,12,2,2,1,2,4,3,3,1,1> total = 6678. More...
 
class  ConvHx4ReluStreamMultiRow< INP_H, INP_W, OUT_W, OUT_W_PAD, STEP_H, STEP_W, B, C, M, KH, KW, GROUP, IS_RELU >
 Vector stream implementation for BCHW, stores biases, requires KH==KW==3, INP_W%4==0, OUT_W_PAD%8==0, STEP_H==1, STEP_W==1, GROUP==1, ConvHx4ReluStreamMultiRow<26,28,24,24,1,1,1,2,4,3,3,1,1> total = 14801. More...
 
class  ConvHx4Out4ReluStream< INP_H, INP_W, OUT_W, OUT_W_PAD, STEP_H, STEP_W, B, C, M, KH, KW, GROUP, IS_RELU >
 Vector stream implementation for OUT_W == 4 < 8, stores biases, requires KW<=3, INP_W%4==0, OUT_W_PAD==4, STEP_H==1, STEP_W==1,. More...
 
class  Conv1x1ReluStream< INP_H, INP_W, OUT_W, OUT_W_PAD, STEP_H, STEP_W, B, C, M, KH, KW, GROUP, IS_RELU >
 Vector stream implementation for BCHW, stores biases, requires KH==KW==1, INP_W%4==0, OUT_W_PAD%(8|4)==0, STEP_H==1|2, STEP_W==1|2, GROUP==1, Conv1x1ReluStream<24,24,24,24,1,1,1,2,4,1,1,1,1> total = 4217. More...
 
class  Conv1x1Out4ReluStream< INP_H, INP_W, OUT_W, OUT_W_PAD, STEP_H, STEP_W, B, C, M, KH, KW, GROUP, IS_RELU >
 Vector stream implementation for OUT_W == 4 < 8, stores biases, requires KH==KW==1, INP_W%4==0, OUT_W_PAD==4, STEP_H==1, STEP_W==1,. More...
 
class  ConvHx4ReluPktStream< INP_H, INP_W, OUT_W, OUT_W_PAD, STEP_H, STEP_W, B, C, M, KH, KW, GROUP, IS_RELU >
 Vector stream implementation for BCHW, stores biases, requires KW<=3, INP_W%4==0, OUT_W_PAD%(8|4)==0, STEP_H==1|2, STEP_W==1|2, GROUP==1,. More...
 
class  Conv1x1ReluPktStream< INP_H, INP_W, OUT_W, OUT_W_PAD, STEP_H, STEP_W, B, C, M, KH, KW, GROUP, IS_RELU >
 Vector stream implementation for BCHW, stores biases, requires KH==KW==1, INP_W%4==0, OUT_W_PAD%(8|4)==0, STEP_H==1|2, STEP_W==1|2, GROUP==1,. More...
 

Detailed Description

Reference performance:

Design notes for non-padded weights

Design notes